Electrical Device and Fabrication Method

ABSTRACT

An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application of U.S. application Ser. No.13/620,955, entitled “Electrical Device and Fabrication Method,” whichwas filed on Sep. 15, 2012, which is a divisional application of U.S.application Ser. No. 12/031,321, now U.S. Pat. No. 8,274,132, entitled“Electrical Device and Fabrication Method,” which was filed on Feb. 14,2008, all of which are incorporated herein by reference.

TECHNICAL FIELD

Embodiments of the present invention relate generally to electricaldevices, and, in accordance with some embodiments, to electrical fusedevices for fin field-effect transistor (FinFET) or silicon-on-insulator(SOI) technologies.

BACKGROUND

Multigate field-effect transistor (MuGFET) devices or fin field-effecttransistor (FinFET) devices are expected to be used in the future due tothe limited down-scaling capability of conventional planar or bulk CMOStechnologies (CMOS: complementary metal oxide semiconductor). A finfield-effect transistor (FinFET) may be understood to mean afield-effect transistor having a fin structure. A fin structure or finmay, for example, include a ridge structure or a bridge structure, whichis formed or freely suspended on a substrate. A multi-gate fieldeffect-transistor (MuGFET) may, for example, include a field-effecttransistor, in which a channel region is driven by two or more gates.

FinFET devices are typically designed for high-speed logic coreapplications featuring low supply voltages (e.g., 0.8 V to 1.2 V). Theprocess development is usually focused on these standard MOSFET devices.The availability of devices beyond standard MOSFET devices and theirintegration into the process flow may contribute to make MuGFET orFinFET technologies interesting for, e.g., System-on-Chip (SOC)applications. Electrical fuses or electrically programmable fuses(E-fuses) are one device class that may be used here.

Programming an electrical fuse may typically be achieved by passing anelectrical current of sufficient magnitude through the fuse for asufficient period of time such that a conductive link (also referred toas a fuse link or fusible link) of the fuse is blown or ruptured,thereby increasing the resistance of the fuse. A sensing circuit may beused to sense the resistance and thus determine the state of the fuse.

E-fuses may, for example, allow for the programming of certain functionsof an integrated circuit such as personalization andactivation/deactivation of functional blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. The drawings are not necessarilyto scale, emphasis instead generally being placed upon illustrating theprinciples of the invention. In the following description, variousembodiments of the invention are described with reference to thefollowing drawings, in which:

FIGS. 1A to 1C show different views of an electrical device inaccordance with an embodiment;

FIG. 2 shows a method for fabricating an electrical device in accordancewith another embodiment;

FIG. 3 shows a method for fabricating an electrical fuse device inaccordance with another embodiment;

FIG. 4 shows a method for fabricating an electrical fuse device inaccordance with another embodiment;

FIGS. 5A to 5C show schematic views illustrating different stages in aselective epitaxial growth process;

FIGS. 6A, 6B and 7A to 7D show different views illustrating a method forfabricating an electrical fuse device in accordance with anotherembodiment;

FIGS. 8A to 8D show an electrical fuse device in accordance with anotherembodiment;

FIGS. 9A to 9D show an electrical fuse device in accordance with anotherembodiment;

FIGS. 10A, 10B and 11A to 11D show different views illustrating a methodfor fabricating an electrical fuse device in accordance with anotherembodiment;

FIGS. 12A to 12D show an electrical fuse device in accordance withanother embodiment;

FIGS. 13A to 13D show an electrical fuse device in accordance withanother embodiment; and

FIG. 14 shows a method for fabricating an electrical fuse device inaccordance with another embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1A shows a schematic perspective view of an electrical device 100in accordance with an embodiment of the invention. FIG. 1B shows a planview of the electrical device 100, and FIG. 1C shows a cross-sectionalview of the electrical device 100 along the line A-A′ in FIG. 1A.

The electrical device 100 includes a fin structure 102. The finstructure 102 includes a first section 102 a that has a first width w₁(indicated by the arrows 105 a in FIG. 1B) and a first height h₁(indicated by the arrows 106 a in FIG. 1C), and a second section 102 bthat has a second width w₂ (indicated by arrows 105 b in FIG. 1B) and asecond height h₂ (indicated by arrows 100 in FIG. 1C), wherein the firstwidth w₁ is smaller than the second width w₂ (i.e., w₁<w₂) and the firstheight h₁ is lower than the second height h₂ (i.e., h₁<h₂). In thiscontext, the “height” of a section of the fin structure 102 may beunderstood to mean the dimension of that section in a directionperpendicular to a surface (e.g., perpendicular to a substrate surfaceor main processing surface), on or above which the electrical device 100or the fin structure 102 is arranged (see FIG. 1C). The “width” of asection of the fin structure 102 may be understood to mean the dimensionof that section in a direction perpendicular to the height andessentially perpendicular to a current flow direction in that section.

In accordance with an embodiment, the fin structure 102 may furtherinclude a third section 102C having a third width w₃ (indicated byarrows 105 c in FIG. 1B) and a third height h₃ (indicated by arrows 106c in FIG. 1C), wherein the second section 102 b and the third section102C are electrically connected with each other via the first section102 a, as shown in FIG. 1A.

In accordance with an embodiment, the third width w₃ may beapproximately the same as the second width (that is, approximately equalto w₂ as shown in FIG. 1B), and/or the third height h₃ may beapproximately the same as the second height (that is, approximatelyequal to h₂ as shown in FIG. 1C), although in accordance withalternative embodiments, the third width w₃ (i.e., the width of thethird section 102 c) may be different from the second width w₂ (i.e.,the width of the second section 102 b) and/or the third height h₃ (i.e.,the height of the third section 102 c) may be different from the secondheight h₂ (i.e., the height of the second section 102 b).

In accordance with one embodiment, the first section 102 a may bearranged between the second section 102 b and the third section 102C, asshown in FIGS. 1A to 1C. Clearly, the second and third sections 102 b,102C may abut the first section 102 a at opposite ends of the firstsection 102 a.

In accordance with some embodiments, the electrical device 100 may bearranged on or above a substrate 101 (as shown in FIG. 1A to FIG. 1C),for example, on or above a semiconductor substrate, e.g., on or above asilicon substrate (for example, a silicon bulk substrate) or asilicon-on-insulator (SOI) substrate in accordance with an embodiment,although other suitable substrates may be used in accordance with otherembodiments. In case that the electrical device 100 is arranged on orabove an SOI substrate, the fin structure 102 may be arranged on aburied oxide (BOX) layer of the SOI substrate and may be formed from athin silicon top layer of the SOI substrate, in accordance with anembodiment. In case that the electrical device 100 is arranged on orabove a silicon bulk substrate, the fin structure 102 may be formed froma silicon layer near the surface of the silicon bulk substrate, inaccordance with an embodiment.

In accordance with another embodiment, the electrical device 100 mayfurther include at least one contact structure (or contact region)connected to and/or abutting the fin structure 102 of the electricaldevice. For example, in accordance with one embodiment, the electricaldevice 100 may include a first contact region 103 formed adjacent to thesecond section 102 b of the fin structure 102 and electrically connectedto the second section 102 b, and a second contact region 104 formedadjacent to the third section 102C of the fin structure and electricallyconnected to the third section 102C, as shown in FIG. 1A to FIG. 1C. Thecontact regions 103, 104 may have a considerably larger width than thefin structure 102, for example, in order to reduce contact resistances.

In accordance with one embodiment, the fin structure 102 may have asymmetrical shape. In other words, the second section 102 b and thethird section 102C of the fin structure 102 may have about the samelength, wherein the length of a section is understood to mean thedimension of the section in a direction perpendicular to the width andto the height of that section. To put it in still other words, the firstsection 102 a of the fin structure 102 may be centered, as shown in FIG.1A to FIG. 1C. In accordance with other embodiments, the fin structure102 may have an asymmetrical shape. That is, the second section 102 bmay have a length that is different from the length of the third section102 c.

In accordance with one embodiment, the third section 102 c may not bepresent. In this case, the first section 102 a of the fin structure 102may be directly connected to the second contact region 104, inaccordance with an embodiment.

In accordance with one embodiment, the fin structure 102 may furtherinclude a fin core structure and a layer formed on the fin corestructure in at least one of the second and third sections 102 b, 102 cof the fin structure 102 (not shown, see FIG. 12A). The fin corestructure may have sidewalls and a top surface, and the layer may, forexample, be formed on the sidewalls and/or on the top surface of the fincore structure in the second and third sections 102 b, 102 c of the finstructure 102. In other words, in the second section 102 b and/or in thethird section 102 c of the fin structure 102, the sidewalls and/or thetop surface of the fin core structure may be covered by the layer.

In accordance with another embodiment, the layer may also be formed onat least one of the first and second contact regions 103, 104.

In accordance with another embodiment, the layer formed on the fin corestructure may be formed (in other words, deposited) by means of aselective epitaxial growth (SEG) process. In other words, the layer maybe an epitaxial layer that has been grown selectively on the fin corestructure.

For example, in accordance with some embodiments, the fin core structuremay include or may be made of a crystalline material, for example, acrystalline semiconductor material such as, e.g., silicon, and the layermay be formed on the fin core structure by growing an epitaxial layer(e.g., an epitaxial silicon layer or an epitaxial silicon-germanium(SiGe) layer in case of a silicon fin core structure) selectively on thecrystalline material of the fin core structure. The crystalline materialof the fin core structure may clearly serve as seed material for the SEGgrowth.

Clearly, in accordance with one embodiment, the fin structure 102 mayinclude a fin core structure that is partially covered by a layer (e.g.,the epitaxially grown layer), wherein an uncovered portion of the fincore structure corresponds to the first section 102 a of the finstructure 102 and wherein the covered portion or portions of the fincore structure correspond to the second section 102 b and (if present)to the third section 102 c of the fin structure 102.

In accordance with one embodiment, the first section 102 a of the finstructure 102 and/or the layer formed in the second and third sections102 b, 102 c of the fin structure 102 (for example, the epitaxiallygrown layer) may be at least partially silicided. In other words, inaccordance with this embodiment, the silicon material of the fin corestructure in the first section 102 a of the fin structure 102 and/or thelayer (e.g., the epitaxially grown silicon layer) formed on the fin corestructure in the second section 102 b and/or in the third section 102 cof the fin structure 102 may be partially silicided (in other words,partially transformed into a silicide) or even fully silicided (in otherwords, fully transformed into a silicide). Furthermore, in accordancewith another embodiment, the fin core structure itself may be partiallyor fully silicided in the second section 102 b and/or in the thirdsection 102 c of the fin structure 102.

In accordance with another embodiment, the second section 102 b of thefin structure 102 may include a first partial fin core structure and/orthe third section 102 c of the fin structure 102 may include a secondpartial fin core structure (not shown, see, e.g., FIG. 7A). Furthermore,the fin structure 102 may include a layer formed on the first and secondpartial fin core structures and further in the first section 102 a ofthe fin structure 102 such that the first and second partial fin corestructures are electrically connected with each other via the layer (notshown, see, e.g., FIG. 7A). Each of the first and second partial fincore structures may have sidewalls and a top surface, and the layer maybe formed on the sidewalls and on the top surface of the first andsecond partial fin core structures, and furthermore between the firstand second partial fin core structures. In other words, the sidewallsand/or the top surface of the first partial fin core structure in thesecond section 102 b of the fin structure 102 and/or the sidewallsand/or the top surface of the second partial fin core structure in thethird section 102 c of the fin structure 102 may be covered by thelayer.

In accordance with one embodiment, the layer may be formed by means of aselective epitaxial growth (SEG) process in a similar manner asdescribed herein above. That is, an epitaxial layer may be grownselectively on the first and second partial fin core structures.

For example, in accordance with some embodiments, the first partial fincore structure and/or the second partial fin core structure may includeor may be made of a crystalline material, for example, a crystallinesemiconductor material such as, e.g., silicon, and the layer may beformed on the first and/or second partial fin core structure(s) bygrowing an epitaxial layer (e.g., an epitaxial silicon layer or anepitaxial silicon-germanium (SiGe) layer in case of a silicon fin corestructure) selectively on the crystalline material of the first and/orsecond partial fin core structure(s).

Clearly, in accordance with one embodiment, the fin structure 102 mayinclude a first partial fin core structure (in the second section 102 b)and/or a second partial fin core structure (in the third section 102 c),wherein the first and/or second partial fin core structures are/iscovered by a layer (e.g., the epitaxially grown layer), and wherein thelayer is also formed between the first and second partial fin corestructures (or between the first partial fin core structure and thesecond contact region 104, if there is no second partial fin corestructure present in the fin structure 102), thereby bridging thedistance between the first and second partial fin core structures (orbetween the first partial fin core structure and the second contactregion 104).

Clearly, in accordance with this embodiment, that portion of the layer(e.g., the epitaxially grown layer) that bridges the space between thefirst and second partial fin core structures (or between the firstpartial fin core structure and the second contact region 104 if nosecond partial fin core structure is present in the fin structure 102),corresponds to the first section 102 a of the fin structure 102 whilethe first and/or second partial fin core structures covered with thelayer (e.g., the epitaxially grown layer) correspond to the secondsection 102 b and/or third section 102 c of the fin structure 102.

In accordance with some embodiments, at least one of the first section102 a, the second section 102 b and the third section 102 c of the finstructure 102 may be at least partially silicided. For example, inaccordance with one embodiment, the first section 102 a (clearly, thelayer (e.g. the epitaxially grown layer) formed between the first andsecond partial fin core structures) may be partially silicided (that is,partially transformed into a silicide). Alternatively, the first section102 a may be fully silicided (that is, fully transformed into asilicide). In accordance with another embodiment, that portion of thelayer (e.g., the epitaxially grown layer) formed on the first and/orsecond partial fin core structure may also be partially or fullysilicided. In accordance with another embodiment, the first partial fincore structure and/or the second partial fin core structure may bepartially or fully silicided.

In accordance with another embodiment, one or more electrical contactsmay be formed on the first contact region 103 and/or on the secondcontact region 104 to electrically contact the first and second contactregions 103, 104.

In accordance with one embodiment, the electrical device 100 may beconfigured as an electrical fuse device, for example, as an electricallyprogrammable fuse (E-fuse), wherein the first section 102 a of the finstructure 102 may include (or form) a fusible link region of the fusedevice. The fuse device may also be referred to as a “FinFuse”. Clearly,the fusible link region of the fuse device has a narrower width and alower height than the other sections of the fin structure 102 such thatthe fusible link region may serve as a rupture or break point of thefuse device, if an electrical current of sufficient magnitude is passedthrough the device.

FIG. 2 shows a method 200 for fabricating an electrical device inaccordance with another embodiment.

In 220, a fin structure is formed on a substrate. A first section of thefin structure has a first width and a first height, and a second sectionof the fin structure has a second width and a second height, wherein thefirst width is smaller than the second width and the first height islower than the second height.

In accordance with one embodiment, the fin structure is formed such thatit further includes a third section having the second width and thesecond height, wherein the second and third sections of the finstructure are electrically connected with each other via the firstsection of the fin structure.

In accordance with another embodiment, forming the fin structureincludes forming a first partial fin core structure and a second partialfin core structure on the substrate, the first and second partial fincore structures being separated by a gap, and forming a layer on thefirst and second partial fin core structures, thereby bridging the gapand forming an electrically conductive link between the first and secondpartial fin core structures. Each of the first and second partial fincore structures may have sidewalls and a top surface, and in accordancewith one embodiment, the layer is formed on the sidewalls and on the topsurface of the first and second partial fin core structures.

In accordance with another embodiment, the first and second partial fincore structures include or consist of a crystalline material, andforming the layer on the first and second partial fin core structuresincludes growing an epitaxial layer selectively on the crystallinematerial of the first and second partial fin core structures.

In accordance with another embodiment, after formation of the layer, thelayer is at least partially silicided.

In accordance with another embodiment, forming the fin structureincludes forming a fin core structure on the substrate and forming alayer on the fin core structure, wherein the formation of the layer isblocked in a portion of the fin core structure that corresponds to thefirst section of the fin structure.

In accordance with another embodiment, the fin core structure includesor is made of a crystalline material, wherein forming the layer on thefin core structure includes growing an epitaxial layer selectively onthe crystalline material of the fin core structure. In other words, thelayer may be formed by means of a selective epitaxial growth (SEG)process.

In accordance with another embodiment, the blocking of the formation ofthe selectively grown epitaxial layer (SEG layer) may be achieved bymeans of a blocking layer for the SEG growth that may be formed on thefin core structure before formation of the SEG layer. In accordance withone embodiment, the blocking layer may be a nitride layer. In accordancewith other embodiments, though, the blocking layer may include or may bemade of other materials.

In accordance with another embodiment, at least one of the blockedportion of the fin core structure and the layer formed on the fin corestructure may be at least partially silicided. In other words, theblocked portion of the fin core structure and/or the layer formed on thefin core structure may be partially or fully silicided. Furthermore, inaccordance with another embodiment, the fin core structure may be atleast partially silicided.

In accordance with another embodiment, the blocking layer (e.g., thenitride layer) may be re-used as a silicide blocking layer during thesilicidation of the layer formed on the fin core structure.

FIG. 3 shows a method 300 for fabricating an electrical fuse device inaccordance with another embodiment.

In 320, a first fin and a second fin are formed on a substrate, thefirst and second fins being separated by a gap.

In 340, an epitaxial layer is grown on the first and second fins suchthat a fusible link region is formed in the gap between the first andsecond fins.

Clearly, the growth of the epitaxial layer on the first and second finsmay lead to the merging of the fins such that an electrically conductiveconnection is formed between the fins by material of the epitaxiallayer.

In accordance with an embodiment, at least one of the fusible linkregion and the epitaxial layer may be at least partially silicided.

In accordance with some embodiments, the fusible link region may have asmaller cross-sectional area than the remaining portions of the firstand second fins. For example, in accordance with one embodiment, thefusible link region may have a smaller width than the remaining finportions. In accordance with another embodiment, the fusible link regionmay have a lower height than the remaining fin portions. In accordancewith still another embodiment, the fusible link region may have both asmaller width and a lower height than the remaining fin portions.

FIG. 4 shows a method 400 for fabricating an electrical fuse device inaccordance with another embodiment.

In 420, a fin is formed on a substrate.

In 440, an epitaxial layer is grown on the fin, wherein a portion of thefin is blocked from the epitaxial growth to form a fusible link regionof the fin.

In accordance with an embodiment, at least one of the fusible linkregion and the epitaxial layer is at least partially silicided.

In accordance with some embodiments, the fusible link region may have asmaller cross-sectional area than the remaining portions of the fin. Forexample, in accordance with one embodiment, the fusible link region mayhave a smaller width than the remaining fin portions. In accordance withanother embodiment, the fusible link region may have a lower height thanthe remaining fin portions. In accordance with still another embodiment,the fusible link region may have both a smaller width and a lower heightthan the remaining fin portions.

FIG. 5A to FIG. 5C show schematic views illustrating three differentstages 520, 540 and 560 of a selective epitaxial growth (SEG) process asmay be applied in a typical FinFET process. It is shown that a materialbridge 505 is formed between a first fin 501 and a second fin 503 by theSEG process. In this context, it is noted that the facet-like SEGgrowth, as shown in FIGS. 5A to 5C, is typical for a <100> crystalorientation. If a different crystal orientation is used (for example, a<110> crystal orientation) as an alternative, the facet-like growth maynot be observed while a similar bridging of the fins may still bepossible.

FIGS. 6A, 6B and 7A to 7D show different views illustrating a method forfabricating an electrical device in accordance with another embodiment.In accordance with this embodiment, an electrical fuse device (orE-fuse) is provided that may, for example, be used in FinFET or SOItechnologies.

FIG. 6A and FIG. 6B show that a first partial fin core structure 651 anda second partial fin core structure 652 are formed on a substrate 601,which, in accordance with the embodiment shown, is asilicon-on-insulator (SOD substrate. In accordance with otherembodiments, different substrates, such as, for example, silicon bulksubstrates, may be used. The SOI substrate 601 may include a buriedoxide (BOX) layer, and the first and second partial fin core structures651, 652 may be formed on the buried oxide layer of the substrate 601.

The first and second partial fin core structures 651, 652 are formedsuch that they are separated by a gap 653. The (shortest) distance “g”between the two partial fin core structures 651 and 652 (in other words,the dimension “g” of the gap 653) is indicated by the double arrow 607.In accordance with one embodiment, the gap “g” may be about less thantwo times the thickness of a layer to be formed on the first and secondpartial fin core structures 651, 652 (see FIG. 7A).

FIG. 6A is a surface-parallel cross-sectional view (in other words, alayout drawing) while FIG. 6B is a longitudinal cross-section along theline B-B′ shown in FIG. 6A. It is noted that in accordance with theembodiment shown in FIGS. 6A and 6B, the first and second partial fincore structures 651, 652 are arranged on the substrate 601 such thatthey have a common longitudinal axis, which coincides with thecross-sectional line B-B′. In accordance with another embodiment, thesecond partial fin core structure 652 may be rotated (around a rotationaxis that is perpendicular to the substrate surface) by an angle φ(e.g., o<φ≦180°) with respect to the first partial fin core structure651, or vice versa.

In accordance with the embodiment shown, the first and second partialfin core structures 651, 652 consist of silicon material with anydoping. In accordance with other embodiments, the first and secondpartial fin core structures 651, 652 may include or may be made of othercrystalline materials, e.g., other semiconductor materials such as, forexample, compound semiconductor materials (e.g., SiGe, GaAs or othermaterials).

A first contact region 603 is formed adjacent to and abuts the firstpartial fin core structure 651, and a second contact region 604 isformed adjacent to and abuts the second partial fin core structure 652.The first and second contact regions 603, 604 may be used toelectrically contact the electrical fuse device to be formed. Inaccordance with the embodiment shown, the first and second contactregions 603, 604 also consist of silicon, although, in accordance withother embodiments the first and second contact regions 603, 604 mayinclude or may be made of other crystalline materials, e.g. othersemiconductor materials. In accordance with one embodiment, the firstand second contact regions 603, 604 may include or may be made of thesame material or materials as the first and second partial fin corestructures 651, 652.

Clearly, FIG. 6A and FIG. 6B show the formation of two separate siliconshapes on the substrate 601, i.e., a first silicon shape including thefirst partial fin core structure 651 and the first contact region 603,and a second silicon shape including the second partial fin corestructure 652 and the second contact region 604, wherein each of thefirst and second silicon shapes has a fin-like extension (i.e., thefirst and second partial fin core structures 651 and 652, respectively),the extensions being adjacent to each other. The first and secondpartial fin core structures 651, 652 may be used to form an active finregion of the electrical fuse device as described hereinbelow.

The first and second silicon shapes may, for example, be formed by useof a standard FinFET or SOI process technology. For example, inaccordance with an embodiment, an SOI wafer material (including asilicon film arranged on or above a buried oxide (BOX) layer) may beused. The silicon film may be structured using, for example, standardlithographical processes (using, e.g., a photomask) and etch processessuch that the adjacent silicon regions, in other words the fin regions(i.e., the first and second partial fin core structures 651, 652) andthe first and second contact regions 603, 604 are formed on thesubstrate 601 (e.g., on the buried oxide layer of the SOI substrate) inaccordance with the layout drawing of FIG. 6A. In accordance with otherembodiments, the first and second silicon shapes may be formed by use ofa silicon bulk technology. For example, in accordance with oneembodiment, a silicon bulk wafer may be used, and a silicon layer nearthe surface of the silicon bulk wafer may be structured in a similarmanner as the silicon film of the SOI wafer as described above.

FIGS. 7A to 7D show that a layer 754 is formed on the first and secondpartial fin core structures 651, 652, thereby bridging the gap 653 andforming an electrically conductive link between the first and secondpartial fin core structures 651, 652. FIG. 7A is a surface-parallelcross-sectional view of the resulting structure 700, while FIG. 7B is alongitudinal cross-section along the line C-C′, FIG. 7C is a transversalcross-section along the line D-D′ and FIG. 7D is a transversalcross-section along the line E-E′ shown in FIG. 7A.

In accordance with the embodiment shown, the layer 754 is a siliconlayer that is formed by means of a selective epitaxial growth (SEG)process. In other words, the layer 754 is an epitaxial silicon layerthat is grown selectively on the crystalline silicon material of thefirst and second partial fin core structures 651, 652. Clearly, thesilicon material of the first and second partial fin core structures651, 652 serves as seed silicon for the SEG growth of the silicon layer754.

In accordance with other embodiments, for example, in case that thefirst and second partial fin core structures 651, 652 include or aremade of other crystalline materials, also the layer 754 may include ormay be made of other crystalline materials. In general, the layer 754may include or may be made of any material or materials that may beepitaxially grown on the material or materials of the first and secondpartial fin core structures 651, 652, wherein the material of thepartial fin core structures 651, 652 may serve as seed material for theSEG growth of the layer 754.

Clearly, by applying a selective epitaxial growth, the two adjacentfin-like extensions (i.e., the first and second partial fin corestructures 651, 652) that were initially separated by the gap 653, aremerged together by the epitaxial layer 754 that grows selectively on thecrystalline material (e.g., the silicon material) of the first andsecond partial fin core structures 651, 652. The epitaxial silicon layer754 grows between the two adjacent partial fin core structures 651, 652and forms a narrow connection or bridge between the formerly adjacentregions (e.g., in a similar manner as illustrated in connection withFIGS. 5A to 5C). Furthermore, the silicon layer 754 grows on all exposedsilicon surfaces (that is, for example, also on the sidewalls and thetop surface of the first and second partial fin core structures 651,652, and on the sidewalls and the top surface of the first and secondcontact regions 603, 604) thereby increasing the thickness and theheight of the silicon shapes. The cross-sectional view shown in FIG. 7Dprovides insight into the composition of the fin region of the firstsilicon shape (that includes the first partial fin core structure 651)after the formation of the SEG layer 754 on the first partial fin corestructure 651.

The thickness t_(SEG) of the epitaxial layer 754 is indicated by thearrows 708 in FIG. 7A. In accordance with one embodiment, t_(SEG) may bein the range from about 50 nm to about 100 nm, although in accordancewith other embodiments, t_(SEG) may have a different value. In general,the layer 754 may be grown with such a thickness that it closes the gap653 between the first and second partial fin core structures 651, 652,or, alternatively the gap 653 may have a dimension that is about lessthan two times the thickness of the epitaxial layer 754 (i.e.,g<2×t_(SEG)), as described above.

Clearly, FIGS. 7A to 7D show an electrical fuse device 700 in accordancewith an embodiment.

The electrical fuse device 700 includes a fin structure 702. The finstructure 702 includes a first section 702 a (defined by that portion ofthe layer 754 that is formed between the first and second partial fincore structures 651, 652) that has a first width and a first height, anda second section 702 b (defined by the first partial fin core structure651 and that portion of the layer 754 that is formed on the firstpartial fin core structure 651) that has a second width and a secondheight. As can be seen from FIGS. 7A to 7D, the first width (i.e., thewidth of the first section 702 a of the fin structure 702) is smallerthan the second width (i.e., the width of the second section 702 b ofthe fin structure 702) and the first height (i.e., the height of thefirst section 702 a) is lower than the second height (i.e., the heightof the second section 702 b). The fin structure 702 further includes athird section 702 c (defined by the second partial fin core structure652 and that portion of the layer 754 that is formed on the secondpartial fin core structure 652) that has approximately the same widthand height as the second section 702 b. The second section 702 b and thethird section 702 c of the fin structure 702 are electrically connectedwith each other via the first section 702 a arranged between the secondand third sections 702 b, 702 c.

Clearly, the first section 702 a of the fin structure 702 includes (ordefines) a fusible link region 712 of the electrical fuse device 700arranged in the center of the fin structure 702. The fusible link region712 is formed by the SEG silicon 754 and has a lower height and anarrower width as compared to the other portions of the fin structure702 (i.e., the second section 702 b and the third section 702 c), as canbe seen from FIG. 7C, which shows a transversal cross-section throughthe fusible link region 712 in the first section 702 a of the finstructure 702, and from FIG. 7D, which shows a transversal cross-sectionthrough the second section 702 b of the fin structure 702, and also ascompared to the contact regions 603, 604.

Although the electrical fuse device 700 in accordance with theembodiment is shown to have a symmetrical fin structure 702 with thefusible link region 712 (or first section 702 a) located in the centerof the fin structure 702, it is noted that in accordance with otherembodiments, the fusible link region 712 (or first section 702 a) may bearranged off-center. In other words, the electrical fuse device 700 mayhave an asymmetrical structure. In still other words, the length of thesecond section 702 b may be different from the length of the thirdsection 702 c.

In accordance with another embodiment, electrical contacts may be formedon or above the first and second contact regions 603, 604 in order toelectrically contact the electrical fuse device 700 (not shown, see,e.g., FIG. 9B). The contacts may, for example, be formed using standardprocesses.

In FIG. 7A to FIG. 7C, the fusible link region 712 is shown to have botha smaller width and a lower height than the other portions (i.e., thesecond and third sections 702 b, 702 c) of the fin structure 702. Inaccordance with other embodiments, though, the fusible link region 712may only have a smaller width or a lower height than the other portionsof the fin structure 702. In accordance with some embodiments, thefusible link region 712 may have a smaller cross-sectional area than thesecond section 702 b and/or the third section 702 c of the fin structure702.

FIG. 8A to FIG. 8D show an electrical fuse device 800 in accordance withanother embodiment. FIG. 8A is a surface-parallel cross-sectional viewof the device 800, while FIG. 8B is a longitudinal cross-section alongthe line F-F′, FIG. 8C is a transversal cross-section along the lineG-G′ and FIG. 8D is a transversal cross-section along the line H-H′shown in FIG. 8A.

The electrical fuse device 800 is different from the electrical fusedevice 700 in that the silicon layer 754 is partially silicided afterits formation. In other words, the silicon layer 754 is partiallytransformed into a silicide 855. To put it in still other words, asilicide layer 855 is formed in or on all exposed surfaces of thesilicon layer 754. By means of the silicidation, the narrow fusible linkregion 712 of the fin structure 702 is fully silicided. In other words,the fusible link region 712 is fully transformed into a silicide 855. Inaccordance with an alternative embodiment, the fusible link region 712of the fin structure 702 may only be partially silicided. In otherwords, by means of the silicidation the fusible link region 712 may beonly partially transformed into a silicide 855. FIG. 8C shows atransversal cross-section through the fusible link region 712 of the finstructure 702 after formation of the silicide 855. As can be seen, thefusible link region 712 is fully transformed into a silicide 855 (inaccordance with an alternative embodiment, the fusible link region mayonly be partially silicided). The cross-sectional view shown in FIG. 8Dprovides insight into the composition of the second section 702 b of thefin structure 702 after the partial silicidation of the silicon layer754.

The electrical fuse device 800 may be fabricated in a similar manner asdescribed above in connection with the electrical fuse device 700, withadditional partial silicidation of the silicon layer 754. In accordancewith an embodiment, the silicidation may be achieved by means of astandard silicidation process. Clearly, the fusible link region 712 ofthe fin structure 702 may be either fully (as shown) or partiallytransformed into a silicide 855 by means of the silicidation process.

FIG. 9A to FIG. 9D show an electrical fuse device 900 in accordance withanother embodiment. FIG. 9A is a surface-parallel cross-sectional viewof the device 900, while FIG. 9B is a longitudinal cross-section alongthe line J-J′, FIG. 9C is a transversal cross-section along the lineK-K′ and FIG. 9D is a transversal cross-section along the line L-L′shown in FIG. 9A.

The electrical fuse device 900 is different from the electrical fusedevice 700 in that the silicon layer 754 is fully silicided after itsformation. In other words, the silicon layer 754 is fully transformedinto a silicide 855 such that the narrow fusible link region 712 in thefirst section 702 a of the fin structure 702 is fully transformed into asilicide 855. FIG. 9C shows a transversal cross-section through thefully silicided fusible link region 712 of the fin structure 702, andthe cross-sectional view shown in FIG. 8D provides insight into thecomposition of the second section 702 b of the fin structure 702 afterthe full silicidation of the SEG layer 754.

In accordance with the embodiment shown in FIGS. 9A to 9D, portions ofthe first and second partial fin core structures 651, 652 and portionsof the first and second contact regions 603, 604 are also transformedinto a silicide 855.

The electrical fuse device 900 may be fabricated in a similar manner asdescribed above in connection with the electrical fuse device 700, withadditional full silicidation of the silicon layer 754. In accordancewith an embodiment, the silicidation may be achieved by means of astandard silicidation process. Cleary, the fusible link region 712 isfully silicided by means of the silicidation process.

In accordance with another embodiment, the first and second partial fincore structures 651, 652 and/or the first and second contact regions603, 604 may also be fully silicided, in other words, entirelytransformed into a silicide (not shown).

The electrical fuse device 900 further includes electrical contacts 934formed on or above the first and second contact regions 603, 604 inorder to make electrical contact to the electrical fuse device 900. Thecontacts 934 may, for example, be formed using standard processes.

FIGS. 10A, 10B and 11A to 11D show different views illustrating a methodfor fabricating an electrical device in accordance with anotherembodiment. In accordance with this embodiment, an electrical fusedevice (or E-fuse) is provided that may, for example, be used in FinFETor SOI technologies.

FIG. 10A and FIG. 10B show that a fin core structure 1050 is formed on asilicon-on-insulator (SOI) substrate 1001. In accordance with otherembodiments, different substrates (e.g. silicon bulk substrates) may beused. The SOI substrate 1001 may include a buried oxide (BOX) layer, andthe fin core structure 1050 may be formed on the buried oxide layer ofthe substrate 1001.

FIG. 10A is a surface-parallel cross-sectional view (in other words, alayout drawing) while FIG. 10B is a longitudinal cross-section along theline M-M′ shown in FIG. 10A.

In accordance with the embodiment shown, the core structure 1050consists of silicon material with any doping. In accordance with otherembodiments, the fin core structure 1050 may include or may be made ofother crystalline materials, e.g., other semiconductor materials suchas, for example, compound semiconductor materials (e.g., SiGe, GaAs orother materials).

A first contact region 1003 is formed adjacent to and abuts one end ofthe fin core structure 1050, and a second contact region 1004 is formedadjacent to and abuts an opposite end of the fin core structure 1050.The first and second contact regions 1003, 1004 may be used toelectrically contact the electrical fuse device to be formed. Inaccordance with the embodiment shown, the first and second contactregions 1003, 1004 also consist of silicon, although, in accordance withother embodiments the first and second contact regions 1003, 1004 mayinclude or may be made of other crystalline materials, e.g., othersemiconductor materials. In accordance with one embodiment, the firstand second contact regions 1003, 1004 may include or may be made of thesame material or materials as the fin core structure 1050.

Clearly, FIG. 10A and FIG. 10B show the formation of a single siliconshape on the substrate 1001 including the fin core structure 1050 andthe first and second contact regions 1003, 1004. Clearly, according tothis embodiment, the primary active fin region of the electrical fusedevice is formed as one piece in contrast to the embodiments describedherein above in connection with FIGS. 6A to 9D.

The single silicon shape may, for example, be formed by use of astandard FinFET or SOI process technology. For example, in accordancewith an embodiment, an SOI wafer material (including a silicon filmarranged on or above a buried oxide (BOX) layer) may be used. Thesilicon film may be structured using, for example, standardlithographical processes (using, e.g., a photomask) and etch processessuch that the fin region (i.e., the fin core structure 1050) and thefirst and second contact regions 1003, 1004 are formed on the substrate1001 (e.g., on the buried oxide layer of the SOI substrate) inaccordance with the layout drawing of FIG. 10A.

FIGS. 11A to 11D show that a layer 1154 is formed on the fin corestructure 1050, wherein the formation of the layer 1154 is blocked in aportion of the fin core structure 1050. FIG. 11A is a surface-parallelcross-sectional view of the resulting structure 1100, while FIG. 11B isa longitudinal cross-section along the line N-N′, FIG. 11C is atransversal cross-section along the line O-O′ and FIG. 11D is atransversal cross-section along the line P-P′ shown in FIG. 11A.

The layer 1154 is a silicon layer that is formed on the fin corestructure 1050 (and also on the first and second contact regions 1003,1004) using a selective epitaxial growth (SEG) process as describedherein above, wherein the silicon material of the fin core structure1050 and the first and second contact regions 1003, 1004 serves as seedsilicon for the SEG process. In accordance with other embodiments, forexample in case that the fin core structure 1050 and/or the first andsecond contact regions 1003, 1004 include or are made of other(crystalline) materials, also the layer 1154 may include or may be madeof other materials. For example, the layer 1154 may include or may bemade of any material or materials that may be grown epitaxially on thematerial of the fin core structure 1050 and/or the contact regions 1003,1004.

As shown, the formation or growth of the epitaxial silicon layer 1154 isblocked in a center portion of the fin core structure 1050. Inaccordance with other embodiments, the formation of the silicon layer1154 may be blocked in a portion of the fin core structure 1050 locatedoff-center.

In accordance with the embodiment shown, the blocking is achieved bymeans of a blocking layer 1160 that is formed on a portion of thesidewalls and the top surface of the fin core structure 1050. Inaccordance with one embodiment, the blocking layer 1160 may be a nitridelayer. In accordance with other embodiments, though, the blocking layer1160 may include or may be made of other materials.

Clearly, by means of the blocking layer 1160 the growth of SEG siliconis locally blocked in a center portion of the fin core structure 1050.In other words, the SEG blocking layer 1160 enables SEG growth only onor above those exposed silicon surfaces that are not covered by theblocking material (e.g., nitride material). The blocking layer 1160 hasa dimension “m” (indicated by the double arrow 1109 in FIG. 11A and FIG.11B) in the direction parallel to the longitudinal axis of the fin corestructure 1050.

Clearly, by applying a selective epitaxial growth, the silicon layer1154 grows on all uncovered portions of the fin core structure 1050(e.g., on all uncovered portions of the sidewalls and the top surface ofthe fin core structure 1050) such that the thickness and height of theseuncovered portions of the fin core structure 1050 are increased.Furthermore, the silicon layer 1154 grows on all exposed siliconsurfaces of the first and second contact regions 1003, 1004.

After the formation of the layer 1154, the SEG blocking layer 1160 maybe removed as is shown in FIG. 12A to FIG. 12D. Alternatively, the SEGblocking layer 1160 may be kept and may serve as a silicide blockinglayer in a subsequent silicidation process as described herein below.

Clearly, FIGS. 12A to 12D show an electrical fuse device 1200 inaccordance with an embodiment, wherein FIG. 12A is a surface-parallelcross-sectional view of the device 1200, while FIG. 12B is alongitudinal cross-section along the line Q-Q′, FIG. 12C is atransversal cross-section along the line R-R′ and FIG. 12D is atransversal cross-section along the line S-S′ shown in FIG. 12A.

The electrical fuse device 1200 includes a fin structure 1202. The finstructure 1202 includes a first section 1202 a (defined by the centerportion of the fin core structure 1050 that was blocked from the SEGgrowth and is thus not covered by the silicon layer 1154) that has afirst width and a first height, and a second section 1202 b (defined bya first portion of the fin core structure 1050 covered by the siliconlayer 1154) that has a second width and a second height. As can be seenfrom FIGS. 12A to 12D, the first width (i.e., the width of the firstsection 1202 a of the fin structure 1202) is smaller than the secondwidth (i.e., the width of the second section 1202 b of the fin structure1202), and the first height (i.e., the height of the first section 1202a) is lower than the second height (i.e., the height of the section 1202b). The fin structure 1202 further includes a third section 1202 c(defined by a second portion of the fin core structure 1050 covered bythe silicon layer 1154) that has approximately the same width and heightas the second section 1202 b. The second section 1202 b and the thirdsection 1202 c of the fin structure 1202 are electrically connected witheach other via the first section 1202 a arranged between the second andthird sections 1202 b, 1202 c.

Clearly, the first section 1202 a of the fin structure 1202 includes (ordefines) a fusible link region 1212 of the electrical fuse device 1200arranged in the center of the fin structure 1202. The fusible linkregion 1212 is formed by blocking the SEG growth in the center portionof the fin core structure 1050 such that the silicon layer 1154 isprevented from growing in that center portion. Thus, the fusible linkregion 1212 (or section 1202 a) of the fin structure 1202 has a lowerheight and a narrower width as compared to the other portions of the finstructure 1202 (i.e., the second section 1202 b and the third section1202 c), as can be seen from FIG. 12C and FIG. 12D which showtransversal cross-sections through the fusible link region 1212 and thesecond section 1202 b of the fin structure 1202, respectively.

Although the electrical fuse device 1200 in accordance with theembodiment is shown to have a symmetrical fin structure 1202 with acentered fusible link region 1212, it is noted that in accordance withother embodiments, the fusible link region 1212 (or the first section1202 a) may be arranged off-center. In other words, the electrical fusedevice 1200 may have an asymmetrical structure.

In accordance with another embodiment, electrical contacts may be formedon or above the first and second contact regions 1003, 1004 in order toelectrically contact the electrical fuse device 1200 (not shown, seee.g. FIG. 13B). The contacts may, for example, be formed using standardprocesses.

In FIG. 12A to FIG. 12C, the fusible link region 1212 is shown to haveboth a smaller width and a lower height than the other portions (i.e.,the second and third sections 1202 b, 1202 c) of the fin structure 1202.In accordance with other embodiments, though, the fusible link region1212 may only have a smaller width or a lower height than the otherportions of the fin structure 1202. This may, for example, be achievedby using an appropriate blocking layer or mask in the blocking of theSEG growth, in accordance with an embodiment. In accordance with someembodiments, the fusible link region 1212 may have a smallercross-sectional area than the second section 1202 b and/or the thirdsection 1202 c of the fin structure 1202.

FIG. 13A to FIG. 13D show an electrical fuse device 1300 in accordancewith another embodiment. FIG. 13A is a surface-parallel cross-sectionalview of the device 1300, while FIG. 13B is a longitudinal cross-sectionalong the line T-T′, FIG. 13C is a transversal cross-section along theline U-U′ and FIG. 13D is a transversal cross-section along the lineV-V′ shown in FIG. 13A.

The electrical fuse device 1300 is different from the electrical fusedevice 1200 in that the silicon layer 1154 is partially silicided afterits formation. In other words, a silicide layer 1355 is formed in or onall exposed surfaces of the silicon layer 1154. By means of thesilicidation, the narrow fusible link region 1212 in the first section1202 a of the fin structure 1202 is fully silicided. In other words, thefusible link region 1212 is fully transformed into a silicide 1355. Inaccordance with an alternative embodiment, the fusible link region 1212may only be partially silicided. In other words, by means of thesilicidation the fusible link region 1212 may be only partiallytransformed into a silicide 1355.

FIG. 13C shows a transversal cross-section through the fully silicidedfusible link region 1212, and the cross-sectional view shown in FIG. 13Dprovides insight into the composition of the second section 1202 b ofthe fin structure 1202 after the partial silicidation of the siliconlayer 1154.

The electrical fuse device 1300 may be fabricated in a similar manner asdescribed above in connection with the electrical fuse device 1200, withadditional partial silicidation of the silicon layer 1154. In accordancewith an embodiment, the silicidation may be achieved by means of astandard silicidation process. The silicidation may either fully (asshown) or partially transform the narrow center portion of the finstructure 1202 into a silicided fusible link region 1212. The length “n”of the fusible link region (indicated by arrows 1310 in FIG. 13A) may bedetermined by the dimension “m” of the blocking layer 1160 (see FIGS.11A and 11B), which may be mask-defined. Thus, the length of the fusiblelink region 1212 may be a function of layout parameters and thus lessdependent on the processing technology.

In accordance with another embodiment, the silicon layer 1154 may befully silicided, in other words, fully transformed into a silicide.Furthermore, in accordance with other embodiments, also the SEG coveredfin and contact regions may be partially or fully silicided. In otherwords, the fin core structure 1050 may be partially or fully silicidedin the second section 1202 b and/or third section 1202 c of the finstructure 1202, and the first and second contact regions 1003, 1004 mayalso be partially or fully silicided.

In accordance with another embodiment, the blocking layer 1160 (e.g., anitride layer used for SEG blocking) may optionally remain on and atopof the fin during silicidation such that a silicidation of the fusiblelink region may be prevented. Thus, an electrical fuse device with anunsilicided fusible link region may be provided.

FIG. 14 shows a method 1400 for fabricating an electrically programmablefuse (E-fuse) using selective epitaxial growth (SEG) in accordance withan embodiment.

As shown in 1402, a silicon-on-insulator (SOI) wafer material may beprovided. The SOI wafer material may include a silicon film arrangedover a buried oxide (BOX) layer.

Furthermore, as shown in 1404, a photomask may be used, and adjacentsilicon regions (“fin regions”) may be formed according to a givenlayout drawing (for example, one of the layout drawings shown hereinabove).

Furthermore, as shown in 1406, various processing steps of a standardprocess flow (e.g., a standard FinFET process flow), e.g., for gatestack formation, gate formation or implantation, may be used inaccordance with an embodiment.

Furthermore, as shown in 1408, a selective epitaxial growth (SEG)process may be applied to merge and overgrow the adjacent silicon finregions.

Furthermore, as shown in 1410, the fusible link region may be silicidedin accordance with an embodiment. Furthermore, the fin regions may bepartially or fully silicided in accordance with an embodiment.

Furthermore, as shown in 1412, contacts may be formed in accordance withan embodiment.

In the following, additional features and potential effects ofillustrative embodiments are described.

FinFET and SOI devices may be highly susceptible to damage by ElectricalOverstress (EOS) or Electrostatic Discharge (ESD) events. Among thereasons for this are both the extremely small geometrical structures ofthe narrow fins (e.g., silicon fins) as well as the strong thermalinsulation of the fins. In accordance with some embodiments, thisproperty is used to provide electrically programmable fuse devices(E-fuse devices) having a reduced programming power.

A reduction of MOSFET source/drain series resistance for FinFETtechnology optimization may be done by the process option of SelectiveEpitaxial Growth (SEG). Silicon may be grown by epitaxy on all exposedsurfaces of an existing silicon shape (also referred to as “seedsilicon”). Such growth of the silicon cross-section is typicallyintended for regular MOS devices for the fin portion between thecontacts and the active channel. As described herein, in accordance withsome embodiments, the SEG is used for the formation of devices with avariable size in fin cross-section and where gaps in the seed siliconare bridged. These devices may also be referred to as “FinFuse” devices.The modulation in silicon cross-section may be used to create high localcurrent densities that may be applied for the programming of E-fuses. Inaccordance with some embodiments, a bridge-region with a narrowcross-section is used as a fusible link between adjacent siliconregions. In accordance with some embodiments, the “FinFuse” may bepartly covered with silicide or may be fully silicided.

An electrical device in accordance with one embodiment includes a finstructure including a first section and a second section, wherein in thefirst section the fin structure has a first width and a first height,wherein in the second section the fin structure has a second width and asecond height, and wherein the first width is smaller than the secondwidth and the first height is lower than the second height.

An electrical device in accordance with another embodiment includes afin structure including a first section and a second section, wherein inthe first section the fin structure has a smaller width and a lowerheight than in the second section.

An electrical device in accordance with another embodiment includes afin structure, wherein a first section of the fin structure is narrowedin at least a first dimension and a second dimension with respect to asecond section of the fin structure, the second dimension beingdifferent from the first dimension.

An electrical fuse device in accordance with one embodiment includes afin structure including a first fin region and a second fin region, anda fusible link region electrically connecting the first and second finregions with each other, wherein in the fusible link region the finstructure has a smaller width and a lower height than in the first andsecond fin regions. In accordance with one embodiment, the fin structureincludes a fin core structure and an epitaxial layer formed selectivelyon the fin core structure in the first and second fin regions. Inaccordance with another embodiment, the first fin region includes afirst partial fin core structure, the second fin region includes asecond partial fin core structure, and the fin structure includes anepitaxial layer formed selectively on the first and second partial fincore structures and in the fusible link region such that the first andsecond fin regions are electrically connected with each other by meansof the epitaxial layer.

In accordance with some embodiments, electrical fuse devices orelectrical fuses (E-fuses) for FinFET or SOI technologies are provided.In accordance with one embodiment, an E-fuse may be formed by the use ofSelective Epitaxial Growth (SEG).

Electrical fuse devices in accordance with some embodiments may includeone or more of the following features.

An electrical fuse device in accordance with one embodiment may befabricated using only existing process steps without introduction ofadditional photo masks. An electrical fuse device in accordance withanother embodiment may have a reduced programming power compared toconventional fuse devices, which may be due to its reduced geometricalsize. The physical core of a fusible link region of an electrical fusedevice in accordance with another embodiment may include or may consistof selectively epitaxially grown silicon (SEG). In accordance withanother embodiment, the SEG-formed regions may be bridging two adjacentsilicon extensions. An electrical fuse device in accordance with anotherembodiment may have a fusible link region that is both narrower andshallower. In accordance with another embodiment, the fusible linkregion of the electrical fuse device may be, by its geometry andmaterial composition, used for significant resistance increase and/orrupture in case that a programming current is injected into theelectrical fuse device.

In accordance with one embodiment, a programmable fuse device for MuGFETor SOI technologies and a fabrication method are provided, including thefollowing features, as outlined below.

Two shapes of silicon (comprising “seed silicon”) are structured suchthat they each define a fin region (fin) and a contact region. The finsare adjacent and define a gap. The seed silicon is overgrown by SEGsilicon. As a consequence, the gap is closed by SEG silicon to form aconductive and fusible link region. The fusible link region may benarrower and/or thinner than the fin regions and the contact regions toallow for self-heating (which may lead to thermal rupture) and increasedcurrent density (which may lead to depletion of material, for example,by electromigration) in the link region.

In accordance with one embodiment, the fusible link region may includeor may be made of silicon.

In accordance with another embodiment, the fusible link region mayinclude or may be made of a silicide material which may have a lowerthermal degradation point compared to silicon. Another effect of asilicided fusible link region may be that electromigration as a fusingmechanism may be supported.

In accordance with some embodiments, forming the narrow and/or shallowfusible link region may be realized by means of partially silicided SEGsilicon or fully silicided SEG silicon.

In accordance with some embodiments, the connecting fin regions may alsobe silicided. One effect of silicided connecting fin regions may be alow-ohmic behavior.

In accordance with another embodiment, a single shape (or piece) ofsilicon (comprising “seed silicon”) is structured such that it defines asingle fin region (fin). The seed silicon is overgrown by SEG silicon,wherein the SEG growth on the fin is prevented (in other words, blocked)locally by application of local SEG blocking (e.g., using a blockinglayer). By means of the SEG growth, those regions of the fin that arenot blocked are increased in their thickness and height, while thethickness and/or height of the blocked region of the fin remainsapproximately unchanged. Thus, the blocked region of the fin may benarrower and/or shallower than the regions of the fin covered with SEGsilicon, such that the blocked region may define a fusible link region.In accordance with some embodiments, the SEG growth may be followed by apartial or full silicidation of the link region and/or the SEG siliconlayer.

In accordance with some embodiments, the used SEG silicon may be astandard part of advanced FinFET technologies. In accordance with oneembodiment, the thickness t_(SEG) of the SEG layer may be in the rangefrom about 50 nm to about 100 nm, although in accordance with otherembodiments, the SEG layer may have a different thickness.

In accordance with another embodiment, the gap “g” (or, in other words,the shortest distance) between the fins formed by seed silicon may beless than about two times the thickness t_(SEG) of the SEG layer (i.e.,g<2×t_(SEG)) to allow for a reliable closing of the gap.

In accordance with one embodiment, an electrical device (for example, anelectrical fuse device) with a fin structure is provided, wherein aportion of the fin structure (for example, a portion of a fin region ofthe fin structure, e.g., a portion of an active fin region) is bothnarrower in width and lower in height than the other portions of the finstructure. The portion with the narrower width and the lower height mayform a predetermined break point or rupture point of the device. Inother words, the fin structure may have a predetermined break point orrupture point in two dimensions.

While the invention has been particularly shown and described withreference to specific embodiments, it should be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims. The scope of the invention is thusindicated by the appended claims and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced.

What is claimed is:
 1. An electrical device comprising: a fin structurecomprising a first section, a second section and a third section; thefirst section comprising a first width and a first height; the secondsection comprising a second width and a second height; and the thirdsection comprising a third width and a third height, wherein the firstwidth is smaller than the second width and the first height is lowerthan the second height, wherein the first width is smaller than thethird width and the first height is lower than the third height, andwherein the second and third sections are electrically connected witheach other via the first section, and wherein the second section of thefin structure comprises a first partial fin core structure, wherein thethird section of the fin structure comprises a second partial fin corestructure, and wherein the fin structure further comprises a layerformed on the first and second partial fin core structures and furtherin the first section of the fin structure, wherein the first and secondpartial fin core structures are electrically connected with each othervia the layer.
 2. The electrical device of claim 1, wherein the layer isformed by a selective epitaxial growth process.
 3. The electrical deviceof claim 1, wherein the layer is an epitaxial layer.
 4. The electricaldevice of claim 2, wherein the layer is partially silicided.
 5. Theelectrical device of claim 2, wherein the layer is fully silicided. 6.An electrical fuse device comprising: a fin structure comprising a firstfin region and a second fin region, and a fusible link regionelectrically connecting the first and second fin regions with eachother, wherein in the fusible link region the fin structure comprises asmaller width and a lower height than in the first and second finregions, wherein the first fin region comprises a first partial fin corestructure, wherein the second fin region comprises a second partial fincore structure, and wherein the fin structure comprises an epitaxiallayer formed selectively on the first and second partial fin corestructures and in the fusible link region, wherein the first and secondfin regions are electrically connected with each other by the epitaxiallayer.